ICE3003: Computer Architecture (Spring 2014)

[Schedule]

The following schedule is tentative and subject to change without notice.

Day Topic Reading Misc.
3/4 (Tue) Course outline
3/6 (Thu) Introduction Chap. 1.1-1.3
3/11 (Tue) Performance and Power Wall Chap. 1.4-1.6
3/13 (Thu) ARM instruction set architecture I Chap. 2.1-2.6
3/18 (Tue) ARM instruction set architecture II Chap. 2.7-2.10
3/20 (Thu) ARM instruction set architecture III Chap. 2.11-2.14
3/25 (Tue) ARM instruction set architecture III Chap. 2.11-2.14
3/27 (Thu) ARM instruction set architecture IV Chap. 2.16-2.18
4/1 (Tue) Exam #1
4/3 (Thu) Arithmetic module I Chap. 3.1-3.4
4/8 (Tue) Arithmetic module II Chap. 3.4-3.8
4/10 (Thu) Processor: datapath & control I Chap. 4.1-4.4
4/15 (Tue) Processor: datapath & control II Chap. 4.1-4.4
4/17 (Thu) Processor: pipelining Chap. 4.5-4.6
4/22 (Tue) Exam #2 (midterm)
4/25 (Thu) No class (midterm exam week)
4/29 (Tue) Processor: hazards and exceptions Chap. 4.7-4.9
5/1 (Thu) Processor: parallelism Chap. 4.10
5/6 (Tue) No class (Buddha's birthday)
5/8 (Thu) Memory: cache Chap. 5.1-5.3
5/13 (Tue) Memory: virtual memory Chap. 5.4 - 5.5
5/15 (Thu) Memory: parallelism and memory hierarchy Chap. 5.8, 5.10-5.12
5/20 (Tue) Memory: summary Chap. 5.1-5.12
5/22 (Thu) Exam #3
5/27 (Tue) Storage Chap. 6.1-6.4
5/29 (Thu) I/O Chap. 6.5-6.8
6/3 (Tue) Parallelism and I/O Chap. 6.9, 6.10, 6.12, 6.13
6/5 (Thu) Parallel programming models Chap. 7.1-7.4
6/10 (Tue) Parallel hardware models Chap. 7.5-7.13
6/12 (Thu) Wrap-up
6/17 (Tue) Exam% #4 (final)



Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.