ICE3028S13.Schedule History

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June 10, 2013, at 04:10 PM by 121.169.40.164 -
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(:cell align=left valign=top :) Project #2 Final Presentation (16:30~)
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(:cell align=left valign=top :) Project #2 Final Presentation (85529, 16:30~)
June 07, 2013, at 04:21 PM by 115.145.179.182 -
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(:cellnr align=center valign=top :) 6/11 (Tu)
(:cell align=left valign=top :) Project #2 Final Presentation (16:30~)
(:cell align=center valign=top :)
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June 04, 2013, at 11:53 AM by 115.145.179.182 -
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(:cell align=left valign=top :) [[Attach:12-membus.pdf|Memory & Bus]] http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:12-membus.pdf|Memory & Bus]]
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(:cell align=left valign=top :) Operating Systems
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(:cell align=left valign=top :) [[Attach:14-os.pdf|Operating Systems]] http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:15-sched.pdf|Scheduling]] http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:16-power.pdf|Power Management]] http://csl.skku.edu/images/new.gif
June 02, 2013, at 02:33 PM by 115.145.179.182 -
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(:cell align=left valign=top :) Class cancelled
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(:cellnr align=center valign=top :) 6/5 (W)
(:cell align=left valign=top :) Scheduling
(:cell align=center valign=top :) Chap. 6
(:cell align=center valign=top :)
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(:cell align=left valign=top :) Project #2 Presentation
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(:cell align=left valign=top :) Scheduling
(:cell align=center valign=top :) Chap. 6
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(:cell align=left valign=top :) Project #2 Presentation
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May 31, 2013, at 08:03 AM by 115.145.179.182 -
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(:cell align=left valign=top :) %red%Final exam%%
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(:cell align=left valign=top :) %red%Final exam%%
May 24, 2013, at 12:07 PM by 115.145.179.182 -
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(:cell align=left valign=top :) [[Attach:11-io.pdf|Input/Output]] (At #85531) http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:11-io.pdf|Input/Output]] (At #85531)
May 24, 2013, at 12:07 PM by 115.145.179.182 -
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(:cell align=left valign=top :) I/O Devices & Debugging
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(:cell align=left valign=top :) [[Attach:13-iodebug.pdf|I/O Devices & Debugging]] http://csl.skku.edu/images/new.gif
May 21, 2013, at 04:12 PM by 115.145.179.182 -
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8!! ICE3028: Embedded Systems Design (Spring 2013)
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!! ICE3028: Embedded Systems Design (Spring 2013)
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(:cell align=left valign=top :) [[Attach:10-armisa.pdf|ARM Instruction Set Architecture]] http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:10-armisa.pdf|ARM Instruction Set Architecture]]
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(:cell align=left valign=top :) [[Attach:12-membus.pdf|Memory & Bus]] http://csl.skku.edu/images/new.gif
May 19, 2013, at 09:24 AM by 115.145.179.182 -
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(:cell align=left valign=top :) [[Attach:10-armisa.pdf|ARM Instruction Set Architecture]] (At #85531) http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:10-armisa.pdf|ARM Instruction Set Architecture]] http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:11-io.pdf|Input/Output]] (At #85531) http://csl.skku.edu/images/new.gif
May 19, 2013, at 09:24 AM by 115.145.179.182 -
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(:cell align=left valign=top :) [[Attach:9-arm.pdf|ARM Processor]] (At #85531) http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:9-arm.pdf|ARM Processor]] (At #85531)
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May 19, 2013, at 04:48 AM by 115.145.179.182 -
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(:cell align=left valign=top :) [[Attach:8-design.pdf|Designing Embedded Systems]]
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May 14, 2013, at 05:22 PM by 115.145.179.182 -
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(:cellnr align=center valign=top :) 5/14 (Tue)
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May 07, 2013, at 05:05 AM by 216.237.31.110 -
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(:cell align=left valign=top :) [[Attach:9-arm.pdf|ARM Processor]] (At #85531)http://csl.skku.edu/images/new.gif
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(:cell align=left valign=top :) [[Attach:9-arm.pdf|ARM Processor]] (At #85531) http://csl.skku.edu/images/new.gif
(:cell align=center valign=top :) Chap. 2
May 07, 2013, at 05:03 AM by 216.237.31.110 -
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(:cell align=left valign=top :) [[Attach:9-arm.pdf|ARM Processor]] (85531 , 15:00 ~)http://csl.skku.edu/images/new.gif
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May 07, 2013, at 01:51 AM by 115.145.179.244 -
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(:cell align=left valign=top :) [[Attach:9-arm.pdf|ARM Processor]] (85531 , 15:00 ~)http://csl.skku.edu/images/new.gif
May 07, 2013, at 12:51 AM by 115.145.179.244 -
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May 07, 2013, at 12:50 AM by 115.145.179.244 -
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!! ICE3028: Embedded Systems Design (Spring 2013)
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8!! ICE3028: Embedded Systems Design (Spring 2013)
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May 04, 2013, at 06:18 AM by 115.145.179.182 -
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May 03, 2013, at 02:54 AM by 115.145.179.244 -
May 03, 2013, at 02:52 AM by 115.145.179.244 -
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May 03, 2013, at 02:52 AM by 115.145.179.244 -
May 03, 2013, at 02:52 AM by 115.145.179.244 -
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(:cell align=left valign=top :) [[Attach:Project2-Candidate.pdf|Project #2 Suggestions]]
May 02, 2013, at 05:01 AM by 115.145.179.182 -
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May 02, 2013, at 05:01 AM by 115.145.179.182 -
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April 30, 2013, at 03:41 PM by 115.145.179.182 -
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April 30, 2013, at 03:41 PM by 115.145.179.182 -
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April 24, 2013, at 11:06 AM by 115.145.179.244 -
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April 06, 2013, at 03:42 PM by 115.145.179.182 -
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April 06, 2013, at 03:18 PM by 115.145.179.182 -
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April 06, 2013, at 03:17 PM by 115.145.179.182 -
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April 04, 2013, at 07:08 AM by 115.145.179.244 -
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March 31, 2013, at 12:30 PM by 115.145.179.182 -
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March 27, 2013, at 02:56 AM by 115.145.179.244 -
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March 26, 2013, at 08:56 AM by 115.145.179.182 -
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March 22, 2013, at 03:32 AM by 115.145.179.244 -
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March 15, 2013, at 06:09 AM by 115.145.179.182 -
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March 13, 2013, at 10:54 AM by 115.145.179.244 -
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March 12, 2013, at 06:44 AM by 115.145.179.182 -
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March 12, 2013, at 06:44 AM by 115.145.179.182 -
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March 08, 2013, at 03:25 AM by 115.145.179.244 -
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March 08, 2013, at 03:24 AM by 115.145.179.244 -
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March 08, 2013, at 02:52 AM by 115.145.179.244 -
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(:cell align=left valign=top :) Lab 6: Project #1: Log Block Scheme
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March 05, 2013, at 01:59 PM by 115.145.179.182 -
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March 05, 2013, at 01:58 PM by 115.145.179.182 -
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March 04, 2013, at 01:10 PM by 115.145.179.182 -
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March 04, 2013, at 01:01 PM by 115.145.179.182 -
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March 04, 2013, at 01:00 PM by 115.145.179.182 -
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March 04, 2013, at 08:35 AM by 115.145.179.244 -
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March 04, 2013, at 08:33 AM by 115.145.179.244 -
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!! ICE3028: Embedded Systems Design (Spring 2013)

!!! [Schedule]

''The following schedule is tentative and subject to change without notice.''

(:table border=0 width=95% align=left :)
(:cellnr width=12% align=center valign=top :) '''Day'''
(:cell width=50% align=center valign=top :) '''Topic'''
(:cell width=20% align=center valign=top :) '''Reading'''
(:cell width=18% align=center valign=top :) '''Misc.'''
(:cellnr align=center valign=top :) 3/4 (M)
(:cell align=left valign=top :) Course outline
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 3/6 (W)
(:cell align=left valign=top :) Introduction to Embedded Systems
(:cell align=center valign=top :) Chap. 1
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 3/11 (M)
(:cell align=left valign=top :) Designing Embedded Systems
(:cell align=center valign=top :) Chap. 1
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 3/13 (W)
(:cell align=left valign=top :) Lab 1: Introduction to the Jasmine OpenSSD Platform
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 3/18 (M)
(:cell align=left valign=top :) Serial ATA (SATA) Interface
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 3/20 (W)
(:cell align=left valign=top :) Lab 2: DummyFTL
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 3/25 (M)
(:cell align=left valign=top :) Serial ATA (SATA) Interface (con'td)
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 3/27 (W)
(:cell align=left valign=top :) Lab 3: Iometer
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/1 (M)
(:cell align=left valign=top :) NAND Flash Memory
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/3 (W)
(:cell align=left valign=top :) Lab 4: TutorialFTL
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/8 (M)
(:cell align=left valign=top :) Flash Translation Layers (FTLs) I
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/10 (W)
(:cell align=left valign=top :) Lab 5: GreedyFTL
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/15 (M)
(:cell align=left valign=top :) Flash Translation Layers (FTLs) II
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/17 (W)
(:cell align=left valign=top :) Lab 6: GreedyFTL (cont'd)
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/22 (M)
(:cell align=left valign=top :) No class (Midterm exam week)
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/24 (Th)
(:cell align=left valign=top :) No class (Midterm exam week)
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 4/29 (M)
(:cell align=left valign=top :) Flash Translation Layers (FTLs) III
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/1 (W)
(:cell align=left valign=top :) Lab 7: GreedyFTL (cont'd)
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/6 (M)
(:cell align=left valign=top :) ARM Processor
(:cell align=center valign=top :) Chap. 2
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/8 (W)
(:cell align=left valign=top :) ARM Instruction Set Architecture
(:cell align=center valign=top :) Chap. 2
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/13 (M)
(:cell align=left valign=top :) Input/Output
(:cell align=center valign=top :) Chap. 3
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/15 (W)
(:cell align=left valign=top :) Invited Talk
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/20 (M)
(:cell align=left valign=top :) Project #2 Proposal
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/22 (W)
(:cell align=left valign=top :) Memory & Bus
(:cell align=center valign=top :) Chap. 4
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/27 (M)
(:cell align=left valign=top :) I/O Devices & Debugging
(:cell align=center valign=top :) Chap. 4
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 5/29 (W)
(:cell align=left valign=top :) Operating systems
(:cell align=center valign=top :) Chap. 4
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 6/3 (M)
(:cell align=left valign=top :) Project #2 Progress report
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 6/5 (W)
(:cell align=left valign=top :) Scheduling
(:cell align=center valign=top :) Chap. 6
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 6/10 (M)
(:cell align=left valign=top :) Power management
(:cell align=center valign=top :) Chap. 6
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 6/12 (W)
(:cell align=left valign=top :) Project #2 Presentation
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 6/17 (M)
(:cell align=left valign=top :) %red%Final exam%%
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:cellnr align=center valign=top :) 6/19 (W)
(:cell align=left valign=top :) -
(:cell align=center valign=top :)
(:cell align=center valign=top :)
(:tableend:)

[[<<]]\\

%frame%''Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.''