SWE3005: Computer Architecture (Fall 2019)

[Schedule]

The following schedule is tentative and subject to change without notice.

Day Topic Reading Misc.
9/3 (Tue) Course outline
9/5 (Thu) Introduction Chap. 1.1-1.3
9/10 (Tue) Performance and Power Wall Chap. 1.4-1.6
9/12 (Thu) No class (Thanksgiving holiday)
9/17 (Tue) ARM instruction set architecture I Chap. 2.1-2.6
9/19 (Thu) ARM instruction set architecture II Chap. 2.7-2.10
9/24 (Tue) ARM instruction set architecture III Chap. 2.11-2.14
9/26 (Thu) ARM instruction set architecture IV Chap. 2.16-2.18
10/1 (Tue) Exam #1
10/3 (Thu) No class (National foundation day)
10/8 (Tue) Arithmetic module I Δ Chap. 3.1-3.4
10/10 (Thu) Arithmetic module II Chap. 3.4-3.8
10/15 (Tue) Processor: datapath & control I Δ Chap. 4.1-4.4
10/17 (Thu) Processor: datapath & control II Chap. 4.1-4.4
10/22 (Tue) Exam #2 (midterm)
10/25 (Thu) No class (midterm exam week)
10/29 (Tue) Processor: pipelining Chap. 4.5-4.6
10/31 (Thu) Processor: hazards and exceptions Chap. 4.7-4.9
11/5 (Tue) Processor: parallelism Chap. 4.10
11/7 (Thu) Memory: cache Δ Chap. 5.1-5.3
11/12 (Tue) Memory: virtual memory Chap. 5.4 - 5.5
11/14 (Thu) Memory: parallelism and memory hierarchy Chap. 5.8, 5.10-5.12
11/19 (Tue) Memory: summary Chap. 5.1-5.12
11/21 (Thu) Exam #3
11/26 (Tue) Storage Δ Chap. 6.1-6.4
11/28 (Thu) I/O Chap. 6.5-6.8
12/3 (Tue) Parallelism and I/O Chap. 6.9, 6.10, 6.12, 6.13
12/5 (Thu) Parallel programming models Δ Chap. 7.1-7.4
12/10 (Tue) Parallel hardware models Chap. 7.5-7.13
12/12 (Thu) Wrap-up
12/17 (Tue) Exam% #4 (final)



Credit: Most of slides for this lecture are based on materials provided by the textbook publisher.